Título: Implementação em Hardware de Redes Neurais Parcialmente Conectadas para Reconstrução de Imagens Tomográficas
Autores: Medeiros, Luciano Frontino de; Silva, Hamilton Pereira da; Ribeiro, Eduardo Parente
Resumo: This article introduces a hardware architecture for the tomographic reconstruction based on partially connected neural network. A programmable logic circuit is designed for the address control unit of EEPROM containing the problem geometry weights and RAM image pixels, coupled to a synchronous arithmetic accumulator for calculating the projections values. This implementation furnishes a conexionist basis for building fast and portable CT equipments.
Palavras-chave: Neural networks; tomography; reconstruction; hardware; programmable logic
Páginas: 6
Código DOI: 10.21528/CBRN2005-101
Artigo em PDF: CBRN2005_101.pdf
Arquivo BibTex: CBRN2005_101.bib